Saturday, January 21, 2017

Building a 68000 Single Board Computer - Books

While there are many excellent web resources on the 68000 microprocessor, this is something of a nostalgia project and printed books still have a lot of appeal. I'd like to mention a few books on the 68000 that I own and have found useful.

Microprocessor Systems Design 68000 Hardware, Software, and Interfacing, Third Edition, by Alan Clements

This is the book that the TS2 design is described in. At almost 1000 pages, it has full coverage of hardware and software for the 68000 series up to and including the 68030. Everything is presenting in logical manner with many diagrams. If you are more interested only in the software side, you can skip the relevant sections. It came with a CD-ROM that includes a number of tools including a 68000 cross-assembler and simulator.

An Introduction to 68000 Assembly Language, by R.A. & J.W. Penfold

This little book represents the opposite end of the spectrum. Aimed at people who might have owned a 68000-based microcomputer like an Apple Macintosh, Commodore Amiga, Atari ST, or Sinclair QL, if presents the basic of 68000 assembly language programming. In it's 100 or so pages it covers the basic programming model, instructions, and address modes and give a few program examples Nothing is specific to a particular computer. It doesn't go into a lot of depth, but meets the goal of a small pocket-sized book that was inexpensive (British Pounds 2.95 at the time).

68000 Assembly Language Programming, Second Edition, Lance A. Leventhal, Doug Hawkins, Gerry Kane, and William D. Cramer.

This book was the 68000 version of a very popular series of books by Osborne that covers assembly language programming (I also have the 6502 version). At almost 500 pages, it provides extensive coverage of the 68000 including architecture, instructions and addressing modes. It includes many diagrams and dozens of detailed basic and advanced code examples. This edition also covers the 68010 and 68020.

On the hardware side I also referred to my Engineer's Notebooks by Forrest M. Mims III to refresh my knowledge on TTL gates and best design practices.

Friday, January 20, 2017

Building a 68000 Single Board Computer - Another Forth

I found another Forth implementation for the 68000 here. This one was distributed by Albert van der Horst from a Forth group in Holland. Unlike eForth that I described in my last blog post, this one
is compatible with the fig-FORTH standard.

It comes with default I/O routines to use a 6850 UART address $10040 (presumably the Motorola ECB), the same as my TS2.

I was able to build it with the VASM assembler with one trivial change. Loading it onto the TS2 over the serial port, it came up and seems to work fine.

Here is a sample session:

TUTOR  1.3 > GO 3648

68000 fig-FORTH V1.0 
1 2 3 4    OK
. 4    OK
+    OK
. 5    OK
* . 1    OK

: STAR 42 EMIT ;    OK


I think it's time to dig out my old copy of Starting Forth by Leo Brodie and refresh my knowledge of this programming language.

Building a 68000 Single Board Computer - Forth

Forth is an interesting programming language. It is an imperative, stack-based, language that the programmer extends by defining new commands. Years ago, I used an in-house developed variant of Forth (we called it Alice) for programming test software. It happened to run on 6809 and 68000 processors.

I looked for available implementations for the 68000 and found a few options. One, for example, was written for early Sun workstations that used 68000 series processors. This was in the 1980s when a Unix workstation with a few megabytes of RAM cost tens of thousands of dollars. I got it to assemble with only a few changes but it relies heavily on calls to the Unix operating system to perform i/o, and would not be easy to port to the TS2. It also looks a little too large for the TS2, wanting to have 96K of memory for storing Forth code.

The Easy68K web site has a copy of this version called eForth. Wrtiten by Bill Muench and C. H. Ting around 1990, this version was adapted by Paul R. Santa-Maria to run on the Motorola MC68000 Education Computer Board (ECB).

Both source code and a S record binary file are in the archive. The binary works perfectly on my TS2, since it is compatible with the ECB.

Here is a short sample session:

TUTOR  1.3 > GO 1000

eForth 68k v1.1
1 .S
1 2 3 4 .S
 1 1 2 3 4
+ ok
 1 1 2 7
* ok
 1 1 14
0 32 DUMP
   0   0  0  4 44  0  0 81 46  0  0 80 30  0  0 80 3A  ___D___F___0___:
  10   0  0 8D E4  0  0 83 AC  0  0 83 B6  0  0 83 C0  ___d___,___6___@
  20   0  0 83 CA  0  0 8C BA  0  0 83 DE  0  0 83 E8  ___J___:___^___h ok

It should build using the VASM assembler with only a few trivial changes, but I didn't need to since it works "out of the box".

Thursday, January 19, 2017

Building a 68000 Single Board Computer - Tiny Basic

Tiny BASIC is a dialect of the BASIC programming language that was originally written by Dennis Allison for early microcomputers including 6502 systems like the KIM-1. It could fit into as little as two or three kilobytes of memory. I earlier blogged about running the 6502 version on my Replica 1 computer.

Tiny Basic spawned a newsletter called Dr. Dobb's Journal of Tiny BASIC Calisthenics and Orthodontia, which evolved into the magazine Dr. Dobb's Journal. In 1985, the 100th issue of Dr. Dobb's Journal published an article by Gordon Brandly describing a Tiny Basic interpreter he had written for the Motorola 68000 microprocessor.

I came across this and thought I would try porting it to my TS2 computer. It turns out that no porting is needed, as it was designed to run on the Motorola MEX68KECB Educational Computer Board, which the TS2 is compatible with. I simply loaded the Motorola S record file and it came up on the console:

TUTOR  1.3 > GO 900

Gordo's MC68000 Tiny BASIC, v1.2


The supported Basic keywords are BYE, CALL, FOR, GOSUB, GOTO, IF, INPUT, LET, LIST, LOAD, NEW, NEXT, PEEK, POKE, PRINT, READ, REM, RETURN, RUN, SAVE, STEP, STOP, AND TO. It is quite a limited version of Basic (it is only about 3K in size!), but some programs have been developed for or ported to it. One that comes with the Tiny Basic distribution is a version of the classic Star Trek game. Here is a transcript of a portion of a game:

Do you want a difficult game?  (Y or N): N
Stardate 3200:  Your mission is to destroy 5 Klingons in 30 stardates.
There are 3 starbases.
Enterprise in Q-75 S-31
Captain: HELP
R=Report       S=SR. sensor   L=LR. sensor
G=Galaxy map   P=Phaser       T=Torpedo
W=Warp engine  * Please use one of these commands *
Captain: R
Status report:
Stardate      3200
Time Left     30
Condition     Green
Position      Q-75 S-31
Energy        4000
Torpedoes     10
Klingons left  5
Starbases     3
Captain: G
Enterprise in Q-75 S-31
Computer display of galaxy map

1:   0   0   0   0   0   0   0   0

2:   0   0   0   0   0   0   0   0

3:   0   0   0   0   0   0   0   0

4:   0   0   0   0   0   0   0   0

5:   0   0   0   0   0   0   0   0

6:   0   0   0   0   0   0   0   0

7:   0   0   0   0   0   0   0   0

8:   0   0   0   0   0   0   0   0
    ..  ..  ..  ..  ..  ..  ..  ..
     1   2   3   4   5   6   7   8

Captain: S
Enterprise in Q-75 S-31
Short range sensor
1 . . . . . . . .
2 . . . . . . . .
3 E . . . . . . .
4 . . . . . . . .
5 . . . . . . . .
6 . . . . . . . .
7 . . . . . . . .
8 . . . . . . . *
  1 2 3 4 5 6 7 8
Captain: L
Enterprise in Q-75 S-31
Long range sensor
   1   7   7
   1   1   1
 101   5   1
Captain: W
Captain: W
Warp engine
Sector distance: 10
Course (0-360): 180
Enterprise in Q-84 S-61
Klingon attack
218 units hit from Klingon at S-63
160 units hit from Klingon at S-51
143 units hit from Klingon at S-21
124 units hit from Klingon at S-12
3305 units of energy left.
Captain: S
Enterprise in Q-84 S-61
Short range sensor
1 . K . . . . . *
2 K . . . . . . .
3 . . . . . . . .
4 . . . . . . . .
5 K . . . . . . .
6 E . K . . . . .
7 . . . . . . . .
8 * . . . . . . .
  1 2 3 4 5 6 7 8
Captain: W
Warp engine
Sector distance: 1
Course (0-360): 0
Spock: "To err is Human."
Enterprise in Q-84 S-61
Klingon attack
242 units hit from Klingon at S-63
172 units hit from Klingon at S-51
189 units hit from Klingon at S-21
 83 units hit from Klingon at S-12
2619 units of energy left.
Shield damaged, 4 stardates estimated for repair
Captain: S
Enterprise in Q-84 S-61
Short range sensor
1 . K . . . . . *
2 K . . . . . . .
3 . . . . . . . .
4 . . . . . . . .
5 K . . . . . . .
6 E . K . . . . .
7 . . . . . . . .
8 * . . . . . . .
  1 2 3 4 5 6 7 8

The article about Tiny Basic was also published in a book: Dr. Dobb's Toolbook of 68000 Programming. I'll have to see if I can find a copy of this.

Wednesday, January 18, 2017

Building a 68000 Single Board Computer - Interrupt Control Circuitry (schematic page 9)


The interrupt circuitry being tested on a breadboard
before it was constructed on the wirewrap board.

The interrupt control circuitry surrounding the 68000 is conventional. A 74LS148 eight line to three line priority encoder, U28, converts the seven levels of interrupt request input into a 3-bit code on IPL0* to IPL2*. Note that each interrupt request input must have a pull-up resistor, except IRQ7* which is always driven by U35A.

The function code from the 68000 is decoded by U32, a 74LS138, and the resulting IACK* output is used to enable a second decoder, U33. U33 is also strobed by AS* and converts the information on A01 to A03 during an IACK cycle into one of seven levels of interrupt acknowledge output (IACK1* to IACK7*). Other function code information supplied by U32 that may be useful in debugging the system is the "user/supervisor" memory access codes and the "program/data" bus cycle codes.

The ABORT switch can generate a level 7 interrupt. This is present on the ECB and with the TUTOR firmware can be used to interrupt program execution. The switch is debounced by cross-coupled NAND gates U34A and U34B and then clocks flip-flop U35A high (it has its data input tied high). The Q* output of the flip-flop goes low, and is connected to the IRQ7* input. Note that, unlike interrupts 1 through 6, a level 7 interrupt cannot be masked or disabled. During an interrupt acknowledge cycle for a level 7 interrupt, IACK7* will go low and clear the flip-flop. The IACK7* signal will also ripple through U7D, U34C and U4F, driving VPA* low to indicate to the 68000 to perform an autovectored interrupt operation. The CPU will then use the level 7 autovector interrupt address in RAM.

Interrupts 5 and 6 are connected to the two ACIAs, allowing interrupt driven i/o to be performed if desired (the TS2 and TUTOR monitor programs do not make use of this). These interrupts are used in the same way on the Motorola ECB board. Like level 7, the interrupts are also configured for autovectored operation. The relevant IACK5* or IACK6* signal will go low and in turn drive VPA* low to perform autovectored interrupt handling.

IRQ4* is also available and configured for autovectored operation. Interrupts IRQ1* through IRQ3* are not -- they could be used with vectored interrupts if external circuitry is added for this.

The interrupt circuitry can be tested from the TUTOR monitor. Pressing the ABORT switch should generate a level 7 interrupt which will produce a "SOFTWARE ABORT" message and register dump.

Pulling IRQ5* or IRQ6* low should cause TUTOR to produce "AV#5 TRAP ERROR" and "AV#6 TRAP ERROR" messages, respectively. In order for this to happen the interrupt mask in the status register must be set to enable these interrupts.

Building a 68000 Single Board Computer - ACIAs (schematic page 8)


The only I/O ports implemented on the TS2 CPU module are the two 6850 ACIAs shown on schematic page 8. The circuit is almost identical to that found in the ECB module. One port is dedicated to the terminal (IC U29 at address $00010040) and the other (IC U30 at address $00010041) is dedicated to the host computer interface.

The baud rate can be selected by selecting the appropriate output of the baud rate generator U31, but there is little reason to use a rate lower than 9600 bps. The two ACIAs can also be run a different baud rates if desired.

Omitted from my design is the serial port transparent mode feature of the original TS2, also present on the ECB, which connected the terminal interface directly to the host port whenever RTS from U29 was high. This means that the TS2 monitor TRAN and TUTOR TM commands will not operate correctly, but the transparent mode is of little use unless the console is actually a dumb terminal rather than a host computer.

An error should be noted on the schematic on page 896 of the Clements book. The chip selects for the ACIAs should be driven by the signal CS_PERI2* and not CS_PERI1* as shown in the book.

My design also replaces the 1488 and 1489 RS-232 line drivers and receivers with an FTDI connector to support FTDI USB to serial devices rather than true RS-232, which would require the connected computer to have RS-232 serial ports. This also removed the need for +12V and -12C power supplies.

Optionally the board it can be powered by USB using either of the FTDI serial ports - a jumper needs to be connected on the port where power is taken from, in which case an external power supply should not be used.

Tuesday, January 17, 2017

Building a 68000 Single Board Computer - DTACK and BERR Control Circuitry (schematic page 7)


Each memory access cycle begins with the assertion of AS* by the 68000 and ends with the assertion of DTACK* (or VPA*) by the addressed device or with the assertion of BERR* by a watchdog timer. Schematic page 7 gives the diagram of the DTACK* and BERR* control circuitry on the CPU module.

Whenever a block of 16 KBytes of memory is selected on the CPU module, one of the four select signals, SEL0* to SEL3*, goes active-low. The output, MSEL, of the NAND gate U19A is then forced active-high. MSEL becomes the ENABLE/LOAD* control input of a 74LS161 4-bit counter, U22. When MSEL=0 (i.e. on-board memory is not accessed), the counter is held in its load state and the data inputs on P0 to P3 are preloaded into the counter, by default 1100. The desired preload value can be set using DIP switches. The Q3 output from the counter is gated, uninverted, through U10B and U7B to form the processor's DTACK* input.

When MSEL goes high the counter is enabled. The counter is clocked from the 68000's clock and counts upward from 1100. After four clock pulses, the counter rolls over from 1111 to 0000 and Q3 (and therefore DTACK*) goes low to provide the handshake required by the 68000 CPU. At the end of the cycle, AS* is negated and MSEL goes low to preload the counter with 1100 and negate DTACK*.

At the same time that U22 begins counting, a second timer, U21 (another 74LS161), also begins to count upward. The count clock is taken from the 68000's E output which runs at CLK/10. This counter is cleared to zero whenever AS* is negated. The rippled output from the counter goes high after the fifteenth count from zero and is inverted by the open-collector gate U4E to provide the CPU with a BERR* input. Therefore, unless AS* is negated within 15 E-clock cycles of the start of a bus cycle, BERR* is forced low to terminate the cycle. Note that the counter is disabled (Cep=0) in the singlestep mode (discussed later) to avoid a spurious bus error exception.

A useful feature of the DTACK* circuit is the addition of a single-step mode, allowing the execution of a single bus cycle (note bus cycle, not instruction) each time a button is pushed. This facility can be used to debug the system by freezing the state of the processor.

One of the inputs to the OR gate U10B is INHIBIT_DTACK. If this is active-high, the output of the OR gate is permanently true and the generation of DTACK* by the DTACK* delay circuit is inhibited. Therefore, a bus cycle remains frozen with AS* asserted, forcing the CPU to generate an infinite stream of wait states.

Two positive-edge triggered D flip-flops, U20A and U23A, control INHIBIT_DTACK. U20A acts as a debounced switch and produces an SS/RUN* signal fro its Q output, depending only on the state of the single-step/run switch. Unfortunately, it would be unwise to use the output of U20A to inhibit DTACK*, because changing from run to single-step mode in mid bus cycle might lead to unpredictable results. Instead, the output of U20A is synchronized with AS* from the processor by a second flip-flop, U23A. The INHIBIT_DTACK signal from U23A is forced high only when AS* is negated at the end of a bus cycle. The 68000 always enters its single-step mode at the start of a new cycle before AS* is asserted.

In the single-step mode, DTACK* pulses are generated manually by pressing the "step" switch. The output of this switch is debounced by flip-flop U20B. A second flip-flop, U23B, generates a single, active-low pulse, SS_DTACK*, each time the step button is pushed. SS_DTACK* is gated in U7B to produce the DTACK* input needed to terminate the current bus cycle.

There are two simple ways of testing the DTACK* control circuits. One is in the free-run mode and is done by connecting, say, SEL0* to AS*, so that a delayed DTACK* is produced for each bus cycle. The single-step circuit can also be tested in this mode. Another procedure is to construct a special test rig for the circuit, which simulates the behavior of the 68000 by providing AS*, CLK, and SEL0* signals.